The scaling requirements of today's electronic devices present a challenge with regard to providing the proper power, ground, signal and/or various other connections to each component within a device. For example, chips with area array interconnections having a pitch of 200 micrometers (μm), or less, are now common. Interconnect structures having a multitude of line paths therethrough are generally used to connect the chips to a printed wire board. Thus, the lines must also be scalable to accommodate such closely-spaced connections on the chips.
Further, to reduce power consumption, lower power applications are being implemented. For example, in conventional data centers, power consumption levels are based on devices operating at voltages typically of about one volt (V) or higher. In order to drive significant power savings, use of lower voltages for multi-core processors, to support power levels of less than one V, such as less than 500 millivolts (mV), e.g., less than 300 mV, can lead to one half to one third the power consumption for data processing operations as compared to conventional systems.
A combination of aggressive scaling and low power levels can undesirably lead to an increased amount of errors. Namely, as will be described below, scaling can lead to an increase in voltage variations, i.e., voltage droop, across the chips. These variations can, in some instances, be a significant milli-voltage drop (i.e., from about 10 mV to about 50 mV, or greater) even for the (reduced) operating power levels, e.g., 300 mV, if not properly architected and designed. Thus, depending on the severity of the voltage droop, transistors or circuits in a chip, a chip stack or across multiple chips may not receive the proper voltage and not operate properly or operate with errors.
For example, FIG. 1 is a cross-sectional diagram illustrating conventional chip integration structure 100. Chip integration structure 100 includes chips 102 and decoupling capacitors 104 having one or more (i.e., power, ground and/or signal) connections 101 to substrate 106. Substrate 106 is, for example, a standard ceramic or organic substrate having one or more (i.e., power, ground and/or signal) connections 107 to printed wire board 108. Substrate 106 contains a plurality of lines therethrough (not shown) interconnecting connections 101 to chips 102/decoupling capacitors 104 and connections 107 to printed wire board 108. Package 110 is present between substrate 106 and printed wire board 108.
As is a common practice, the power and ground connections are typically separated from one another by at least one signal connection. Thus, for example, if the connections to substrate 106 are at a 200 μm pitch, then a distance between the power and ground connections is two times the pitch, or 400 μm. This area array input/output (I/O) distancing practice along with typically limited X-Y power and ground cross-sectional size for power grids on a chip, as well as more simultaneous switching transistors drawing power per unit area (as lithographic advancements are made in each new technology node) can limit scalability. Furthermore the evolving drive to miniaturization and performance scaling with through-silicon-vias and thinned die stacking can further magnify the power delivery and voltage droop problem with scaling of each new technology node.
As highlighted above, with scaling, on chip voltage droop becomes a significant factor. Namely, it is difficult to maintain a uniform voltage from the printed wire board through the substrate to the chips when x- and y-line dimensions (see FIG. 1) of the substrate are reduced. As voltage droop gets larger (especially in the context of reduced operating power levels) proper chip operation is at risk and more errors can occur. By way of example only, high level transistor switching can lead to many tens of mV droop in power and a risk of chip malfunction due to a supply voltage of one V. Therefore, the risk for operation at less than 500 mV is even greater. Decoupling capacitors, such as decoupling capacitors 104, can be implemented to accommodate a certain level of voltage fluctuations even with large numbers of simultaneous switching circuits. However, as scaling requirements force feature sizes to get increasingly smaller and the number of circuits per unit area and volume continues to scale with lithographic advancements within one silicon strata level and thinned silicon, and with three-dimensional (3D) stacked chip structures leading to ever more circuits per unit volume, the capabilities of the decoupling capacitors on chip and off chip can be exceeded.
Therefore, chip integration techniques that can accommodate both scaling and reduced power operations without the associated voltage droop problems would be desirable.